With the continued scaling of IC technology, due to the large amount of electronic circuits on a small area, the density of chip input/output connection pads (I/O's) continues to increase. This leads to an increasing bandwidth of interconnects between integrated circuits (IC's) and/or other system elements. For short interconnects, electrical signal lines maintain the highest capacity and speed. In order to keep up with the increasing speed and density requirements, system in a package (SIP) technology is increasingly used. This creates the need for 3-dimensional interconnects.
Three-dimensional (3D) integration requires the realization of electrical interconnections that go through the bulk of the substrate (wafer) whereon or wherein the active devices are realized. These are the so-called Through-Si-Via (TSV) connections. One particular approach to realizing TSV connections is the so-called via-middle approach, where the TSV is realized after the fabrication of the active devices (whereby the fabrication of the active devices is referred to as the front-end-of-line, FEOL), just before the integration of the multilayer chip interconnect stack (whereby the integration is referred to as the back-end-of-line, BEOL). The electrically conductive material of the TSV is typically copper or tungsten metal.
However in the state of the art there are still key issues which need to be resolved in order to integrate these TSV connections in a reliable way with good device performances:                The use of a metallic connection through the silicon substrate results in large mechanical stress levels in the silicon substrate, causing mobility variations in the silicon (Si) resulting in performance degradation of neighboring devices.        The presence of a relatively large metallic structure through the bulk of the substrate causes a relatively large electrical capacitance that degrades circuit performance.        An electrostatic field due to a potential and charging current of the TSV-substrate capacitor during transient operation may affect the device performance of neighboring devices.        
Consequently, there is room for improved TSV interconnections and methods for integrating them.